1. Field of the Invention
This invention relates to integrated circuits and, more particularly, to processes for fabricating high-aspect-ratio contact plugs, which are particularly useful in dynamic random access memories having stacked capacitors.
2. State of the Art
The business of producing dynamic random access memory (DRAM) devices is a very competitive, high-volume business. Process efficiency and manufacturability, as well as product quality, reliability, and performance, are the key factors that determine the economic success of such a venture.
Each cell within a DRAM device, an individually addressable location for storing a single bit of digital data, is comprised of two main components: a field-effect access transistor and a capacitor. Each new generation of DRAM devices generally has an integration level that is four times that of the generation which it replaced. Such a quadrupling of the number of devices per chip is always accompanied by a decrease in device geometries, and often by a decrease in operating voltages. As device geometries and operating voltages are decreased, the DRAM designer is faced with the difficult task of providing reliable, low-resistance electrical interconnections on the chip, increasing device operating speeds, and maintaining cell capacitance at an acceptable level. This must be accomplished without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process.
During integrated circuit manufacture, it is common for contact openings to be etched through an insulative layer down to a diffusion region to which electrical contact is to be made. In a conventional contact formation process, titanium metal is sputtered over the wafer so that the exposed surface of the diffusion region is coated. The titanium metal is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited, coating the walls and floor of the contact opening. Chemical vapor deposition of tungsten or polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) follows. In the case of tungsten, the titanium nitride layer provides greatly improved adhesion between the walls of the opening and the tungsten metal, in addition to preventing attack of the substrate and the formation of xe2x80x9cwormholesxe2x80x9d by tungsten hexafluoride, the precursor compound typically used for tungsten deposition. In the case of the polysilicon, the titanium nitride layer acts as a barrier against dopant diffusion from the polysilicon layer into the diffusion region.
Several factors have been responsible for an increase in contact aspect ratios. Given the need to maintain cell capacitance as the cell area dedicated to each cell on a wafer is shrunk, it has been necessary to employ three-dimensional capacitors for DRAMs of the 4-megabit generation and beyond. Although trench capacitors fabricated in the substrate have been utilized by several manufacturers, most have chosen to employ stacked capacitors (i.e., stacked above the substrate). Because stacked capacitors normally employ vertically oriented capacitive layers, the stack height (i.e., the vertical distance from the substrate to the top of an insulating layer overlying the capacitive layers) has been increasing significantly with each new generation of stacked capacitor DRAMs. The increasing stack height coupled with the decreased area on the substrate to which electrical contact must be made has mandated an increase in contact aspect ratios (contact aspect ratio being the ratio of contact depth to contact opening width).
As decreasing device geometries shrink the substrate area available for making contact to transistor source/drain regions (i.e., the contact landing pad), circuit designers are utilizing self-aligned contacts with increasing frequency. A self-aligned contact is one in which the contact plug is immediately adjacent a transistor gate spacer. With a self-aligned contact structure, the pitch between transistor gates can be narrowed, as the entire landing pad is utilized for making contact to the substrate. Thus, for a given pitch, contact resistance is minimized and reliability is enhanced. A self-aligned contact requires that the gate electrode be coated with a dielectric material that is largely unaffected by the anisotropic plasma contact etch through the interlevel dielectric layer.
The use of self-aligned contacts encourages the use of minimum-photolithographic-pitch layouts. A minimum-pitch layout coupled with the high-aspect-ratio contacts that result in DRAM devices having stacked capacitors is not a good candidate for conventional contact formation, as contact between the small substrate landing pad and the contact conductive material must be particularly sound. For the 256-megabit generation of DRAMs, contacts having contact aspect ratios of greater than 5:1 will likely be the norm. With contact openings having such high-aspect-ratios, sputtering is ineffective at coating the bottom of the contact opening with titanium metal, as it tends to deposit primarily near the mouth of the opening such that the size of the opening becomes narrowed. The narrowing effect reduces the amount of titanium that can be deposited at the bottom of the opening. Since the bottom of the opening is also restricted in size by the use of a self-aligned contact, electrical contact to the substrate is typically poor. Although it is possible to collimate sputtered metal, thereby decreasing the buildup of sputtered material near the mouth of the contact opening and thereby increasing the amount of material that can be deposited at the bottom of the contact opening, deposition rates drop dramatically and deposition times correspondingly increase as collimator aspect ratios increase. At collimator height-to-width aspect ratios of only 2.5:1, deposition rates on the wafer are nearly zero, with most metal atoms being deposited on the collimator. Thus, the collimators must be cleaned with a frequency that is annoying, if not unacceptable, in a production environment. To date, the solutions proposed for this problem have required manufacturing process flows of increased complexity, which invariably tend to decrease product yield and increase product costs. For example, silicided polysilicon buried digit lines (a buried digit line is located at a level below that of the stacked capacitors) have been almost universally adopted by DRAM manufacturers as a solution to high-aspect-ratio digit line contacts. The downside of using a silicided polysilicon buried digit line is that the increased resistance, as compared with that associated with a metal digit line, results in longer information access times. In addition, a buried digit line process typically requires two additional masking steps. Another solution to the problem is to use a polysilicon plug which makes contact to the substrate landing pad and a superjacent metal plug which makes contact to the polysilicon plug. The metal plugs are then strapped with a low-resistance metal interconnect. The downside of such a process flow is added complexity and increased product cost.
What is needed is a simplified DRAM process flow which takes advantage of a self-aligned contact for reduced pitch and greater chip density, and which is compatible with high-aspect-ratio contacts. Such a process and resulting structure will enhance device speed by permitting the use of a metal interconnect structure on top of the cell capacitors.
This invention is a process for manufacturing a dynamic random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride-coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal, which is in contact with the substrate, and with titanium nitride, which is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.
The DRAM process begins after field oxide and gate oxide formation with the patterning of word lines (i.e., the access transistor gates and gate interconnect lines) from a sandwich consisting of a lower layer of doped polysilicon, a middle layer of a refractory metal silicide (e.g., titanium silicide, tungsten silicide, cobalt silicide), and an upper layer of silicon nitride. Following word line formation, spacers are formed on the vertical edges of the word lines by anisotropically etching a subsequently deposited conformal silicon nitride layer. Following the formation of transistor source/drain regions (preferably through several implantation steps), a stacked capacitor is constructed above each source/drain which functions as a storage-node junction. During, following, or during and following the construction of the stacked capacitors, an interlevel silicon dioxide-based dielectric layer such as boro-phospho-silicate glass (xe2x80x9cBPSGxe2x80x9d) is deposited and preferably employed to planarize the array above the level of the stacked capacitors. Contact openings which are self aligned to the silicon nitride transistor spacers are then etched through the BPSG layer to each of the transistor source/drain regions in the substrate which will function as an access-node junction. Each of the contact openings is lined, first with titanium metal, and later with titanium nitride. Both the titanium metal and the titanium nitride layers are deposited via chemical vapor deposition, which provides greatly improved step coverage over sputter deposition methods. During a subsequent anneal step, the titanium metal which is in contact with each of the junctions at the bottom of the contact openings is converted to titanium silicide. The contact openings are then filled with tungsten metal via a further chemical vapor deposition reaction. The tungsten which deposited on top of the interlevel dielectric layer is removed via either a chemical mechanical polishing step or an etch-back step. Metal digit line interconnects which contact the appropriate tungsten plugs are then patterned from a sputtered aluminum alloy layer.